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vitesse semiconductor corporation page 1 7/24/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation datasheet v sc835 2.5 gbits/sec 34x34 crosspoint switch with signal detection g52270-0, rev. 4.1 features general description the VSC835 is a monolithic 34x34 asynchronous crosspoint switch, designed to carry broadband data streams at up to 2.5 gbit/s. the non-blocking switch core is programmed through a parallel port interface that allows random access programming of each output port. a high degree of signal integrity is maintained through the chip through fully differential signal paths. the crosspoint function is based on a multiplexer tree architecture. each data output is driven by a 34:1 multiplexer tree that can be programmed to one and only one of its 34 inputs, and each data input can be routed to multiple outputs. the signal path is unregistered, so no clock is required for the data inputs. the signal path is asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input. each input channel and each output channel has an signal monitor function that can be used to identify loss of activity (loa). an interrupt pin is provided to signal loa, after which an external controller can query the chip to determine the channel(s) on which the fault occurred. each output driver is a fully differential switched current driver with on-die back-terminations for maxi- mum signal integrity. data inputs are terminated on die through 50 ohm resistors terminated to v term . the parallel interface uses ttl levels, and provides address, data, and control pins that are compatible with a microprocessor-style interface. the control port provides access to all chip functions, including loa and programming. program buffering is provided to allow multiple program assignments to be queued and issued simultaneously via a single configure command. VSC835 block diagram ? 34 input by 34 output crosspoint switch ? 2.5 gbits/sec. nrz data bandwidth ? ttl compatible m p interface ? differential pecl data inputs ? on-chip 50 w input terminations ? 50 w source terminated pecl output drivers ? single 3.3v supply ? 14w maximum power dissipation ? high performance 256 bga package control logic m p interface a0 y0 a33 y33
vitesse semiconductor corporation datasheet VSC835 2.5 gbits/sec 34x34 crosspoint switch with signal detection page 2 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 7/24/00 g52270-0, rev. 4.1 figure 1: detailed block diagram functional description data paths all input data must be differential and biased to pecl levels. on-chip terminations are provided, with a nominal impedance of 50 ohms. all input termination resistors are tied to v term . data outputs are provided through differential current switches with on-chip terminations that produce a pecl level output swing. the drive level of the output circuit is designed to produce standard pecl levels when terminated in 50 ohms to 2.0 volts. other termination voltages are possible, such as to vcc or 1.3 volts, but the voltage level of the output will be shifted from its nominal value. the common-mode voltage of the out- put swing can be adjusted using the vcom pins. the adjustment range is not calibrated, but typically allows for +/- 200mv of adjustment in common-mode voltage. the vcom pin self-biases to a nominal value when left unconnected. output channels can be powered off in pairs if fewer than 34 outputs are required. by connecting the vee pin associated with a given pair of outputs to vcc, the output pairs will pull to vcc and chip power will be reduced by approximately 300mw per pair. a,an[33:0] control interface data[5:0], addr[5:0] ale, csb, wrb, rdb intb, monclk, config y,yn[33:0] 34 loa monitor 34 x 34 switch core program memory output drivers
vitesse semiconductor corporation page 3 7/24/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation datasheet v sc835 2.5 gbits/sec 34x34 crosspoint switch with signal detection g52270-0, rev. 4.1 programming interface the switch core is programmed through a parallel interface circuit that allows random reads or writes to the program memory array. the program memory array is buffered to allow multiple programming instructions to be loaded simultaneously with the config pin. parallel programing can be clocked at up to a 50mhz rate and state read-back can be performed at up to 25mhz. the program data is composed of two parts: output address and input address. the output address, denoted by addr[5:0], specifies which output channel is to be programmed. the input address, denoted by data[5:0], specifies which input port the switch slice should connect to. the format of the program data is simple binary. for example: addr[5:0] (000100) / data[5:0] (000110) would direct output channel y4 to connect to input channel a6. the programming state may be verified (read back) by applying the address of the desired output and asserting rdb. the programming state is unknown at power-on. additional address space is provided for access to the monitor registers (see sections below). the microprocessor interface consists of the following sig- nals. levels are ttl (see dc characteristics) : loss of activity (loa) monitoring the loa function consists of an activity monitor on each input channel, connected directly to the pads. the state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying the address 1 of the monitor register corresponding to the signal of interest and asserting rdb. each monitor register is four bits in length, covering the state of four inputs. there is one extra two-bit monitor for the 33 rd and 34 th inputs. the state of each monitor is transferred to the register on the rising edge of monclk, where- upon the activity monitor is cleared until more activity is detected. table 1: programming interface signal table pin i/o description d[5:0] b bidirectional data bus to transfer data to/from internal program registers a[5:0] i address bus to select internal program registers for read-write operations ale i ale functionality is not implemented at this time. tie this pin high. csb i chip select (active low): assert this pin whenever the part is being read or programmed. wrb i write (active low): program data will be transferred to the first level internal registers on the rising edge of this signal (when csb is also low). rdb i read (active low): program data from the internal program or monitor registers will be read out on the data bus when this signal goes low (with csb also low). intb o interrupt (active low): this signal is asserted when an loa condition is found config i configure (active high): assert this signal to transfer queued program information from the first-level internal registers to the second-level registers, making the programming take effect. this signal may be tied high to leave the second-level registers transparent so all programming will take effect immediately. csb must be active (low) when config is asserted. config may be tied to a high- order bit of the address bus monclk i monitor states are transferred to monitor registers on the rising edge of this signal. monclk is not expected to exceed 3mhz. 1. see memory map table
vitesse semiconductor corporation datasheet VSC835 2.5 gbits/sec 34x34 crosspoint switch with signal detection page 4 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 7/24/00 g52270-0, rev. 4.1 if any change in a monitor state occurs after sampling by monclk, an interrupt will be signalled by asserting intb, and the user must identify the offending channel by reading the monitor states. the interrupt will be cleared when the corresponding activity monitor is read, but the monitor state will not be changed. if multiple monitors have triggered the interrupt, it will persist until all the corresponding monitors have been read. loa requires a minimum signal level of 30-150mv peak-peak to recognize an input as active. this is required to distinguish noise on an unconnected signal (where both inputs float to the termination voltage) from activity on a live signal. a minimum of two transitions defines activity. the threshold signal level is controlled by the voltage on the vhys pin. in order to keep the hysteresis in a useful range, it is recommended that vhys be nominally tied to vcc (useful range is 2.0v to vcc ). . ac characteristics note: unless otherwise stated, all specifications are guaranteed but not tested. note 1: skew between any two input channels to a given output. note 2: skew between any two output channels from the same input channel. note 3: required for high-speed output rise/fall spec at f rate =2.5 gbits/s. for lower rate signals, use 0.375/f rate note 4: broadband jitter added to a jitter-free signal; jitter is primarily in the form of isi for random data table 2: memory map address access description 00h r/w output y0s programmed input channel (write and then assert config to program) 01h r/w output y1s programmed input channel ... ... ... 21h r/w output y33s programmed input channel 22h, 23h r/o rx signal monitor for inputs [a0-a3], [a4-a7] (logic 1=no activity) 24h, 25h r/o rx signal monitor for inputs [a8-a11], [a12-a15] 26h, 27h r/o rx signal monitor for inputs [a16-a19], [a20-a23] 28h, 29h r/o rx signal monitor for inputs [a24-a27], [a28-a31] 2ah r/o rx signal monitor for inputs [a32-a33] table 3: data path parameter description min typ max units f rate data rate - - 2.5 gbits/s t iskw input channel delay skew (1) - 300 - ps t oskw output channel delay skew (2) - 300 - ps t r , t f high-speed input rise/fall times, 20% to 80% (3) - - 150 ps t r , t f high-speed output rise/fall times, 20% to 80% - - 150 ps t jp output data eye jitter, peak-peak, 2 31 prbs (4) - - 100 ps
vitesse semiconductor corporation page 5 7/24/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation datasheet v sc835 2.5 gbits/sec 34x34 crosspoint switch with signal detection g52270-0, rev. 4.1 figure 2: figure 2: interrupt timing (change in monitor state registers) figure 3: figure 3: interrupt timing (no change in monitor state registers) figure 4: figure 4: program timing monclk monitor state monitor state reg intb monclk monitor state monitor state reg intb adr[5:0] d[5:0] csb wrb rdb config t scsb t swrb t hwrb t sconfig
vitesse semiconductor corporation datasheet VSC835 2.5 gbits/sec 34x34 crosspoint switch with signal detection page 6 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 7/24/00 g52270-0, rev. 4.1 note 1: measured from falling edge. note 2: measured from rising edge. dc characteristics (over the specified operating conditions) note: icc specified with outputs terminated with 50 ohms to +2.0v and chip vterm=+2.0v, vcc = 3.45v table 4: programming port interface timing parameter description min max units t config switch configuration delay - 6 ns t pdaddr data read propagation delay from addr - 30 ns t pdrdb data read propagation delay from rdb (1) - 7 ns t pdint interrupt propagation delay from monclk (2) - 50 ns t pdstate monclk to internal state register change delay (2) - 6 ns t srdb addr to rdb setup time 5 - ns t hrdb rdb to addr hold time 3 - ns t swrb wrb setup time (for either addr or data) 5 - ns t hwrb wrb hold time (for either addr or data) 3 - ns t sconfig wrb to config setup time 1 - ns t scsb csb setup time (to either wrb or rdb) 0 - ns t pwconfig config pulse width (high) 10 - ns t pwwrb wrb pulse width (low and high) 10 - ns t pwrdb rdb pulse width (low and high) 10 - ns t tsdata data tri-state delay (from either rdb or csb) (2) - 10 ns table 5: power parameter description (max) units i cc v cc supply current 4060 ma p t total chip power 14 w i term-v v term supply current with v term =v cc -1.3v ~0 ma i term-e v term supply current with v term =v cc -2.0v -950 ma
vitesse semiconductor corporation page 7 7/24/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation datasheet v sc835 2.5 gbits/sec 34x34 crosspoint switch with signal detection g52270-0, rev. 4.1 note 1: nominal pecl mode, vcc=vccp=3.3v, vee=0, terminated 50ohms to +2.0v table 6: control port input levels (ttl) parameter description min typ max units conditions v ih input high voltage (ttl) 2.0 3.5 v v il input low voltage (ttl) 0 0.8 v i ih input high current (ttl) 500 m av in = 2.4v i il input low current (ttl) -500 m av in = 0.5v v oh output high voltage (ttl) 2.4 3.0 v i oh = 2ma v ol output low voltage (ttl) 0.1 0.4 v i ol = 1.5ma i oz tri-state output current (ttl) -100 100 m av out = 0.4v-2.4v table 7: data input levels (differential pecl) parameter description min typ max units conditions v id input differential voltage 400 1000 mv v icm input common-mode voltage 1.8 2.2 v v cc =3.3v table 8: data output levels (differential pecl) parameter description min typ max units conditions v od output differential voltage 600 1000 mv note 1 v ocm output common-mode voltage 1.8 2.2 v note 1
vitesse semiconductor corporation datasheet VSC835 2.5 gbits/sec 34x34 crosspoint switch with signal detection page 8 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 7/24/00 g52270-0, rev. 4.1 absolute maximum ratings power supply voltage ( v cc ) potential to gnd ............................................................................-0.5 v to +4.0 v ttl input voltage applied ................................................................................................... -0 .5 v to vcc+0.5 v ecl input voltage applied .................................................................................................. -0. 5 v to v cc +0.5 v output current ( i out ) .............................................................................................................................. ..... 50 ma input current ( i in ) ............................................................................................................................... ....... 50 ma v term current ( i term ) ............................................................................................................................ 800 ma case temperature under bias ( t c ) ................................................................................................-55 o to + 125 o c storage temperature ( t stg ) ...........................................................................................................-65 o to + 150 o c note: caution: stresses listed under absolute maximum ratings may be applied to devices one at a time without causing per- manent damage. functionality at or exceeding the values listed is not implied. exposure to these values for extended periods may affect device reliability. operating conditions supply voltage ( v ee ) .............................................................................................................................. ........... 0 v supply voltage ( v cc ) .............................................................................................................................+ 3.3v 5% supply voltage ( v ccp ) ...........................................................................................................................+3. 3v 5% termination voltage ( v term )...................................................................................................................v cc -1.3v case temperature operating range ( t )................................................................................................ 0 o to 85 o c esd ratings proper esd procedures should be used when handling this product. the VSC835 is rated to the following esd voltages based on the human body model: 1. all pins are rated at or above tbd.
vitesse semiconductor corporation page 9 7/24/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation datasheet v sc835 2.5 gbits/sec 34x34 crosspoint switch with signal detection g52270-0, rev. 4.1 figure 5: i/o equivalent circuits pad v term pad pad i sig 50 50 50 15 i sig pecl input equivalent circuit pecl output equivalent circuit pad vee 2000 vcom (l or r) input equivalent circuit 1300 vcc pad vee 5000 vhys input equivalent circuit 5000 vcc 2500
vitesse semiconductor corporation datasheet VSC835 2.5 gbits/sec 34x34 crosspoint switch with signal detection page 10 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 7/24/00 g52270-0, rev. 4.1 package pin descriptions the VSC835 is packaged in a 27x27mm 256 pin ball grid array package. the 256 bga package is ther- mally enhanced and carries the high-speed signals over controlled impedance lines from the solder ball to the circuit die. the following sections describe the pinout and mechanical details of the VSC835. figure 6: functional pinout floorplan 34:1 switch slice a0 a1 a2 a3 a4 a33 a32 a5 y0 y1 y2 y3 y33 34:1 switch slice 34:1 switch slice 34:1 switch slice programming i nterface i/p los and termination i/p los and termination control logic y32 34:1 switch slice 34:1 switch slice y31 34:1 switch slice
vitesse semiconductor corporation page 11 7/24/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation datasheet v sc835 2.5 gbits/sec 34x34 crosspoint switch with signal detection g52270-0, rev. 4.1 figure 7: pinout diagram vcc vee vterm y6 y8 y10 y20 y22 y26 adr2 adr5 ale 1 a9 a11 a15 d3 d2 d1 d0 intb wrb csb rdb y29 vcomr vhys adr0 adr1 adr3 adr4 y12 y24 y28 a5 d5 y27 y25 y23 y15 y13 y11 y9 a14 a12 a10 a8 vcoml 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a b c d e f g h j k l m n p r t u v w y ball grid index bottom view monclk a3 a1 a7 a13 d4 a17 config a19 a21 a23 a25 a27 a29 a31 a33 y33 y31 y21 y19 y17 y7 y3 y5 y1 y32 y30 y18 y16 y14 y4 y0 y2 a2 a0 a4 a6 a16 a20 a18 a22 a24 a26 a28 a32 a30
vitesse semiconductor corporation datasheet VSC835 2.5 gbits/sec 34x34 crosspoint switch with signal detection page 12 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 7/24/00 g52270-0, rev. 4.1 table 9: package pin identification signal name pin function level high speed data inputs a0, na0 c17, d17 data input pecl a1, na1 v17, u17 data input pecl a2, na2 a17, a16 data input pecl a3, na3 y17, y16 data input pecl a4, na4 d16, c16 data input pecl a5, na5 u16, v16 data input pecl a6, na6 c15, d15 data input pecl a7, na7 v15, u15 data input pecl a8, na8 a15, a14 data input pecl a9, na9 y15, y14 data input pecl a10, na10 d14, c14 data input pecl a11, na11 u14, v14 data input pecl a12, na12 c13, d13 data input pecl a13, na13 v13, u13 data input pecl a14, na14 a13, a12 data input pecl a15, na15 y13, y12 data input pecl a16, na16 d10, c10 data input pecl a17,na17 v9, u9 data input pecl a18, na18 c9, d9 data input pecl a19, na19 y9, y8 data input pecl a20, na20 a9, a8 data input pecl a21, na21 u8, v8 data input pecl a22, na22 d8, c8 data input pecl a23, na23 v7, u7 data input pecl a24, na24 c7, d7 data input pecl a25, na25 y7, y6 data input pecl a26, na26 a7, a6 data input pecl a27, na27 u6, v6 data input pecl a28, na28 d6, c6 data input pecl a29, na29 v5, u5 data input pecl a30, na30 c5, d5 data input pecl a31, na31 y5, y4 data input pecl a32, na32 a5, a4 data input pecl a33, na33 u4, v4 data input pecl
vitesse semiconductor corporation page 13 7/24/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation datasheet v sc835 2.5 gbits/sec 34x34 crosspoint switch with signal detection g52270-0, rev. 4.1 high speed data outputs y0, yn0 e18, e17 data output pecl y1, yn1 e3, e4 data output pecl y2, yn2 e20, f20 data output pecl y3, yn3 e1, f1 data output pecl y4, yn4 f17, f18 data output pecl y5, yn5 f4, f3 data output pecl y6, yn6 g18, g17 data output pecl y7, yn7 g3, g4 data output pecl y8, yn8 g20, h20 data output pecl y9, yn9 g1, h1 data output pecl y10, yn10 h17, h18 data output pecl y11, yn11 h4, h3 data output pecl y12, yn12 j18, j17 data output pecl y13, yn13 j3, j4 data output pecl y14, yn14 j20, k20 data output pecl y15, yn15 j1, k1 data output pecl y16, yn16 k17, k18 data output pecl y17, yn17 k4, k3 data output pecl y18, yn18 l18, l17 data output pecl y19, yn19 l3, l4 data output pecl y20, yn20 l20, m20 data output pecl y21, yn21 l1, m1 data output pecl y22, yn22 m17, m18 data output pecl y23, yn23 m4, m3 data output pecl y24, yn24 n18, n17 data output pecl y25, yn25 n3, n4 data output pecl y26, yn26 n20, p20 data output pecl y27, yn27 n1, p1 data output pecl y28, yn28 p17, p18 data output pecl y29, yn29 p4, p3 data output pecl y30, yn30 r18, r17 data output pecl y31, yn31 r3, r4 data output pecl y32, yn32 r20, t20 data output pecl y33, yn33 r1, t1 data output pecl table 9: package pin identification signal name pin function level
vitesse semiconductor corporation datasheet VSC835 2.5 gbits/sec 34x34 crosspoint switch with signal detection page 14 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 7/24/00 g52270-0, rev. 4.1 programming port adr0 d12 program data address ttl adr1 c12 program data address ttl adr2 b11 program data address ttl adr3 c11 program data address ttl adr4 d11 program data address ttl adr5 a11 program data address ttl d0 y11 program data ttl d1 u11 program data ttl d2 v11 program data ttl d3 w11 program data ttl d4 v12 program data ttl d5 u12 program data ttl ale a10 address latch enable (active high) ttl intb y10 interrupt (active low) ttl rdb w10 read enable (active low) ttl wrb u10 write enable (active low) ttl config w9 configuration strobe (active high) ttl csb v10 chip select (active low) ttl monclk b10 loss of activity monitor clock (active high) ttl power supplies vcc a1, a2, a3, a18, a19, a20, b1, b2, b3, b18, b19, b20, c1, c2, c3, c18, c19, c20, d1, d2, d3, d18, d19, d20, u1, u2, u3, u18, u19,u20, v1, v2,v3,v18, v19, v20, w1, w2, w3, w18, w19, w20, y1, y2, y3, y18, y19, y20 power +3.3v vee b4, b6, b8, b9, b13, b14, b16, b17, d4, e2, e19, h2, h19, m2, m19, t3, t4, w5, w7, w8, w13, w14, w16, w17 power gnd vee f19 power for output channels 0,2 gnd vee g19 power for output channels 4,6 gnd vee j19 power for output channels 8,10 gnd vee k19 power for output channels 12,14 gnd vee l19 power for output channels 16,18 gnd table 9: package pin identification signal name pin function level
vitesse semiconductor corporation page 15 7/24/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation datasheet v sc835 2.5 gbits/sec 34x34 crosspoint switch with signal detection g52270-0, rev. 4.1 vee n19 power for output channels 20,22 gnd vee p19 power for output channels 24,26 gnd vee r19 power for output channels 28,30 gnd vee t19 power for output channel 32 gnd vee f2 power for output channels 1,3 gnd vee g2 power for output channels 5,7 gnd vee j2 power for output channels 9,11 gnd vee k2 power for output channels 13,15 gnd vee l2 power for output channels 17,19 gnd vee n2 power for output channels 21,23 gnd vee p2 power for output channels 25,27 gnd vee r2 power for output channels 29,31 gnd vee t2 power for output channel 33 gnd vterm b5, b7, b12, b15, w4, w6, w12, w15 termination power +2.0v misc. vcoml t18 slicing level for y0 - yn16 (even) analog vcomr c4 slicing level for y1 - yn15 (odd) analog vhys t17 loss of activity hysteresis threshold analog table 9: package pin identification signal name pin function level
vitesse semiconductor corporation datasheet VSC835 2.5 gbits/sec 34x34 crosspoint switch with signal detection page 16 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 7/24/00 g52270-0, rev. 4.1 package information dimensional references ref. min. nom. max. a a1 d d1 e e1 m b c aaa e 1.95 26.80 27.00 27.20 24.13 (bsc.) 20 0.85 1.25 0.25 1.27 typ. n 256 ccc 0.25 1.80 1.65 0.75 1.15 0.65 1.05 0.60 0.65 0.70 26.80 27.00 27.20 24.13 (bsc.) 0.15 p g 0.40 f 0.50 notes: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a b c d e f g h j k l m n p r t u v w y detail b bottom view -a- 0.10 -b- top view 11 d e (4 plcs) c a1 4 detail b b g g 27mm 256 bga package drawing
vitesse semiconductor corporation page 17 7/24/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation datasheet v sc835 2.5 gbits/sec 34x34 crosspoint switch with signal detection g52270-0, rev. 4.1 ordering information the order number for this product is formed by a combination of the device number, and package type. notice vitesse semiconductor corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. therefore the reader is cautioned to confirm that this datasheet is current prior to placing orders. the company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a vitesse product. warning vitesse semiconductor corporations product are not intended for use in life support appliances, devices or systems. use of a vitesse product in such applications without the written consent is prohibited. VSC835 ub device type VSC835: 2.5 ghz 34x34 crosspoint switch package style ub: 256 pin bga package with signal monitoring
vitesse semiconductor corporation datasheet VSC835 2.5 gbits/sec 34x34 crosspoint switch with signal detection page 18 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 7/24/00 g52270-0, rev. 4.1

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